Effect of Jitter on Signal Analysis

Description

The purpose of this project was to design an interconnect consisting of a single trace route across three FR4 layers characterized for a quasi-PCI Express 7.0 serial data link. The PCle 7.0 signal is routed through the trace and analyzed under realistic conditions from the SIE standpoint in this report. A combination of on-chip trace (OCT), on-chip bonding pad (OCP), and a gold bond wire connected to the opposing PCB Bonding pad are used to route the signal out of the chip.  All traces are copper. 

Project Report